Data processing systems typically contain a central processing unit, or processor, to manage the movement of information, or data, between different peripheral devices coupled to the processor. To manage the movement of data, data processing systems typically accept requests for data from user-controlled input devices, access data from data storage devices, modify data within a central processing unit, and store data back to data storage devices. Data processing systems can vary in size and scope, from small systems totally contained within the one or more circuit boards to large systems transferring large blocks of data between numerous devices separated by great distances. In turn, the central processing unit can vary in size and scope from small microprocessors to large host processing units.
The central processing unit, or processor, within the data processing system typically serves as the central, controlling means for managing the system. The processor controls the surrounding components, circuits, memories, and/or devices. The processor receives signals and information from the peripherals, makes decisions based on this information, and takes actions based on these decisions. In some instances, the actions taken by the processor involve providing responses to the peripheral devices.
Information is transferred between the processor and the peripheral devices by typically sending data through transmission lines, which interconnect the processor and the peripheral devices. Information consists of communication signals and/or data bytes and may be transferred bi-directionally, in either direction, over the transmission lines. Synchronization signals, or clocking signals, often accompany the communication signals and/or data bytes sent from the transmitting device to the receiving device. These synchronization, or clocking, signals coordinate the timing of the transmitted information between the transmitting and receiving device and validate the data on the transmission lines. These signals notify the receiving device that the signal line or data bus contains valid information and cause the receiving device to latch the information on the signal line or data bus.
The clock signals must be synchronized, in time, with the data when transferred from the transmitting device to the receiving device. That is, the validating edge of the clock pulse must properly align with an interval in time in which the data bus contains valid data. This timing synchronization is straight-forward at the transmitting device. Circuitry at the transmitting device can be designed to properly align the clock signal and the valid data. However, aligning the clock signal and the valid data at the receiving device is a more difficult problem. Transmission delays may skew the clock signal relative to the data byte. Current clocking techniques use a clock pulse which is narrower in time than the time period for valid data to overcome the time skew incurred during data transmission. The clock signal is commonly one-half the time interval for valid data.
Other factors increase the time skew problem at the receiving device: using a single clock signal for the transfer of multiple data bytes, lengthening the distance between the transmitting and receiving devices, and increasing the speed of data transmission. If the time skew between the clock signal and the data becomes too large at the receiving device, the clock pulse attempts to validate the data bus at a point where the data is an invalid value, or where the data corresponds to an incorrect byte in the transfer sequence.
Current techniques for transferring data from a transmitting to a receiving device use a single clock signal to synchronize multiple data bytes. Using a single clock pulse compounds the time skew problem. Typically, the second data byte will be skewed differently in time at the receiving device than the first data byte or the clock signal. Narrowing the clock pulse can only partially resolve this increased time skew problem at the receiving device. In turn, shorter clock pulses require a higher frequency, or faster, clock signal for the same data rate. Efficient data transfer systems minimize the difference in clock frequency and data rate.
Current data transfer systems also require the data to be transmitted over longer distances between the transmitting and receiving devices. Longer transmission distances increase the time skew between the data and the clocking signal at the receiving device. As stated earlier, increased time skew creates data validity problems at the receiving device. The validating edge of the clock pulse may align with a point on the data bus where the data is either invalid or the wrong data byte in the transfer sequence. Furthermore, efficient data transfer systems require a higher data rate, which requires a faster clock signal. Increasing the clock speed reduces the width of the clock pulse. A smaller clock pulse combined with a larger time skew compounds the problem of data validity at the receiving device.
Data transfer systems often use a parity bit to detect data errors occurring when the data is transmitted between the transmitting and receiving devices. One ordinarily skilled in the art understands that the parity bit is an effective technique for detecting data transmission errors and is commonly used in data transfer systems. The transmitting device typically generates a parity bit specific to each data byte transmitted and separately latches the parity bit onto the data bus. The parity bit accompanies the data byte from the transmitting device to the receiving device and is latched onto the data bus of the receiving device by the clock signal. In turn, the receiving device uses the same technique to check the parity of each data byte received and compares this expected parity to the actual parity of the received data byte. If the parity values are not equal, a parity error is flagged, denoting an error occurred during the transmission of the data.
Accordingly, a method and system is needed to provide an improved clock signal that validates data at the receiving device such that time skew between the data and the clock signal during data transmission is minimized. The present invention uses a parity bit location within a data bus to transmit a clock signal between a transmitting device and a receiving device. Using the parity bit to send the clock signal minimizes the time skew between the clock signal and the data occurring during data transmission, provides higher data transfer rates, and allows longer distances between the transmitting and receiving devices. The present invention also uses an alternate means for detecting data transmission errors since the parity bit is no longer used to detect these errors.